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Personal Web Page:  http://vivekchaturvedi.weebly.com/
Email: vchat001@fiu.edu     v.chaturvedi05@gmail.com
Education:
Florida International University Ph.D Electrical Engineering April 2013
Syracuse University M.S. Electrical Engineering August 2008
RGPV, Bhopal India B.E. Electronics and Communication June 2006
Research Interests: Power/Thermal Aware Real-Time Scheduling, Advanced Computer Architecture, VLSI Design, Pre/Post – Silicon Verification/Validation, Energy Efficient Cloud Computing
Research Projects: Research Projects:

  • Power Aware Scheduling for Real-Time Embedded Systems (Funded by NSF): The goal of this project is to study the stringent power/energy constraints on real-time embedded systems. Particularly, we are interested in developing system level novel tasks scheduling schemes to match the power/energy consumption thresholds without affecting the desired timeliness of task sets.

Contributions:

Developed an Accurate and Reliable System Power and Thermal Models for Single Core and Multicore Architectures

Using a Novel, Fast, Light Weight and Accurate System Level Energy Estimation Method, Conducted a Comparative Study of Various Energy Efficient Task Scheduling Methods

Developed an Efficient and Fast Synthetic Simulation Platform using MATLAB, C++, Perl

Developed a Practical Simulation Platform Combining, Architecture Level Simulators, SimpleScalar and HotSpot, to Test Different Scheduling Techniques with Industry Standard Benchmarks

 

  •  Leakage Aware Temperature-Constrained Scheduling for Real-Time Embedded Systems (Funded by NSF): The research objective of this project is to address the temperature and power/energy consumption issues in real-time embedded systems, with a special focus on the adverse impact of the strong relationship between temperature, leakage power and over all power consumption on the performance of microprocessors.

Contributions:

Incorporating Critical Leakage-Temperature Dependency into System Models Developed an Effective Scheduling Scheme “M-Oscillations” to Minimize the Peak Temperature of the Processors.

Proposed Several Fundamental Principles to Minimize the Peak Temperature on Single Core Processors

Addressed Issues Related to Performance Optimization under Maximum Temperature Constraints

Closely Studied the Neighboring Effects on the Thermal Dynamics of a Core on Multicore Processors

Developed Task Feasibility Analysis Methods on Multicore Processors

Developed Simulation Platform using C++, MATLAB, Perl, HotSpot and SimpleScalar to Validate the Accuracy and Effectiveness of Proposed Algorithms and Theorems

 

  • Power/Thermal Efficient 3D-Multicore System Designs: This is an on-going project focusing on the development of better system level resource management methods to address power/thermal efficiency in 3D stacked multicore architectures. The goal is to develop novel dynamic thermal management and energy minimization techniques employing better task scheduling and speed selection methods. We also seek to develop thermal-aware 3D architectures incorporating novel cooling strategies like inter-tier liquid cooling.
Internship Experience Validation Intern (Micro-Electronics Group), SUN Microsystems, Burlington, MA, USA, Summer-2007

  • Simulation and Debug of Processors and ASIC’s in the High End Server System: This experience provided an opportunity to work in the state of the art verification environment at Sun Microsystems. The task was to work in collaboration with other engineers in validating the next generation CMT processors.

Responsibilities and Contributions:

Performed Post-Silicon Validation on the IO Subsystem to Verify Protocols

Error Injection and Detection on Service Links

Bug Reporting and Result Documentations

Coding in C++, TCL on UNIX Platform

Developed Testing Codes for Validation
Publications: JOURNALS: J1)   V. Chaturvedi, H. Huang, S. Ren, G. Quan, “On the Fundamentals of Leakage Aware Real-Time DVS Scheduling for Peak Temperature Minimization”, Journal of Systems Architecture (JSA), Vol. 58, No. 10, 387-397, 2012J2)   H. Huang, V. Chaturvedi, G. Quan, “Leakage Aware Scheduling On Maximum Temperature Minimization For Periodic Hard Real-Time Systems”, Journal of Low Power Electronics (JOLPE), Vol. 8, No. 4, 378-393, 2012 J3)   G. Quan, V. Chaturvedi, “Feasibility Analysis for Temperature-Constraint Hard Real-time Periodic Tasks”, IEEE Transactions on Industrial Informatics (TII), Vol. 6, No. 3, 329-339, 2010 J4)   H. Huang, V. Chaturvedi, G. Quan, “Throughput Maximization for Periodic Real-Time Systems under the Maximal Temperature Constraint”, IEEE Transactions on VLSI. (under review) CONFERENCES:C1) V. Chaturvedi, G. Quan, “Leakage Conscious DVS Scheduling for Peak Temperature Minimization”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 2011 pg. 135-140 (Acceptance ratio: 30.7%)C2) V. Chaturvedi, H. Huang, G. Quan, “Leakage Aware Scheduling On Maximal Temperature Minimization For Periodic Hard Real-Time Systems”, The 7th IEEE International Conference on Embedded Software and Systems (ICESS), Bradford, UK, June 29-July 01, 2010, pg. 1802-1809 (Acceptance ratio 28%)C3) V. Chaturvedi, P. Thanarungroj, C. Liu, G. Quan, “Validation of Scheduling Techniques to Reduce Peak Temperature on an Architectural Level Platform Set-up”, IEEE SoutheastCon, 2011, Nashville, TN, 111-116

C4) M. Fan, V. Chaturvedi, S. Sha, G. Quan, “Thermal-Aware Energy Minimization for Real-Time Scheduling on Multi-core Systems”, IEEE Real-Time Systems Symposium (WiP-RTSS), 2012, San Juan, PR, USA

C5) M. Fan, V. Chaturvedi, S. Sha, G. Quan, “Feasibility Analysis for Temperature Constrained Real-Time Scheduling on Multi-Core Platforms”, IEEE/ACM Design Automation Conference (wip-DAC), 2013

C6) M. Fan, V. Chaturvedi, S. Sha, G. Quan, “Energy Calculation for Multi-core Systems with Leakage and Temperature Consideration”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2013, (submitted)