CCLI: Novel Instruction Material Development for Embedded System Education in Undergraduate Curriculum

Funding Source: NSF,  $150,000,  3/1/2007 – 9/30/2011
Industrial Support:   Xilinx University Program 

Gang  Quan
Electrical and Computer Engineering, Florida International University


The primary focus of this three-year project is the development of laboratory materials for undergraduate students in embedded system design. The primary goal in developing these materials is to provide the students with extensive hands-on opportunities to enhance their knowledge and understanding of advanced concepts and principles in designing current and next-generation embedded systems using FPGA technology. FPGA design has a much short design cycle, lower cost, and a smoother learning curve.  In addition, FPGA devices are programmable and reprogrammable, which makes them reusable throughout the lab practices and excellent devices to test and investigate different design alternatives, which makes them much more suitable to build Intellectual Property (IP) based application-specific systems in an undergraduate embedded system design course.  FPGA devices are also becoming increasingly popular in industrial embedded system designs where they are often used to develop a piece of “core” functionality which can then be sold as an IP component.  Therefore, learning to use the tools and design processes for FPGA based embedded systems will provide students with skills and experiences that can be readily applied when they begin to compete in the global labor force. We are developing the instructional materials based on the exemplary materials provided by Xilinx University Program (XUP). Our previous experiences have shown that the original material cannot be effectively used in undergraduate embedded system design course due to two major drawbacks: (1) the fundamental concepts are usually buried among a plethora of technical details in the commercial software and hardware environment; (2) the original material is inadequate and insufficient in terms of scope and topic in undergraduate embedded system design education. It is therefore our goal to develop a series of systematic and comprehensive labs and support materials that are suitable for an undergraduate embedded system design education.

Project Objective

To develop lab materials for embedded sem design course, based on the state of the art commercial hardware and software platforms,  that can provide our undergraduate students with extensive hands-on opportunities and valuable experiences in design of current and the next-generation embedded systems.

Lab Environment

Hardware Platform


  Xilinx XUPV5-LX110T Development Platform



Xilinx Virtex-II Pro Development Platform



Xilinx ISE 9.1/10.1    •Xilinx EDK 9.1 /10.1    • Xilinx Chipscope 9.1/10.1    • GNU C


Lab Contents

The principle of FPGA design and embedded system design  

Counter design with VHDL on FPGA, simple embedded system design based on the Board  Support Package (BSP), embedded system design flow.

Embedded system hardware development

Assembly programming for MicroBlaze, hardware platform configuration,build/add customized IPs to an existing design Processor architecture, Platform-based design, memory and I/O devices.

Embedded system software development

Cross-platform software environment configuration, simple embedded software development using C simple embedded application development, cross-platform development, embedded software design flow, software design optimization, hardware/software interfacing.

Real-time operating system supports

Process/thread, multitasking, real-time scheduling, inter process communication (mutex/semaphore/message queue), real-time operating system.

Embedded system debug

Software debugging using EDK debugging tools (XMD and SDK), hardware debugging using ModelSim and Xilinx Chipscope; hardware/software codebug using Xilinx Chipscope.

Advanced embedded system designs

Multicore system implementation; customized clock control IP design and dynamic frequency scaling, RTOS support for multi-core platform, power management, network on chip.


This project is supported by NSF under grant DUE- 1002436, FIU Tech Fee Project 09-024, and Xilinx University Program (XUP).

Florida International University