National Science Foundation (NSF), $201,000,  2010 – 2013
Investigator: Dr. Gang Quan

This project is in collaboration with Dr. Shangping Ren from the Illinois Institute of Technology.


As transistor feature size continuously shrinks and is approaching its physical limit, hardware and software developers are now facing great challenges, one of which is the manufacturing yield problem, that is, the reduced feature size (down to nanometers) has increased the number and density of devices on a single die, resulting in, once again, a decreased fabrication yield. For example, without considering defect tolerance during the architecture design phase, the yield of Cell processors can be as low as 20% to 10%. Another serious concern is the process variation as it can cause maximum clockable frequency and power dissipation to vary from the target design from core to core and chip to chip. For example, Intel circuit research lab showed in 2004 that for 1000 sample chips using 180nm technology, the frequency variation can be as much as 30% while the leakage difference can be 20X among different chips. Precise manufacturing control becomes quite difficult, if not impossible.

In addition, the manufacturing defects and process variations further exacerbate the difficulty of software development and maintenance complexity, especially for mission-critical real-time embedded applications. In the presence of defects and process variations on many-core chips, software developers can no longer assume the underlying hardware architecture is unified and deterministic under the same design. Therefore, a paradigm shift is required in the way we design and develop real-time embedded systems.

collab research application aware


Figure 1  With virtualization, hardware defects and performance variances in the many-core platforms are transparent for the OS and application software. Reconfiguration for virtualization is done using the advanced built-in self test module which includes both test and configuration phases.


The goal of this project is to develop efficient and effective many-core virtualization techniques for real-time embedded applications to tackle the problem of hardware non-determinism caused by manufacturing defects and process variations. Virtualization refers to the techniques for hiding the physical characteristics of computing resources from the way in which they are used by other systems, applications, or end users. The virtualization not only provides operating systems and programmers with a unified interface, but also maintains the feasibility of real-time applications. As shown in Fig. 1, we envision that future many-core processors will be equipped with advanced built-in self test and reconfiguration module, which not only detects the defective architectural components, but also reconfigures the physical chip to mirror the virtualized architecture, based on information such as real-time system characteristics, run-time profiling (including power, temperature) information from previous runs, and other design constraints. Through the virtualization, the physical architecture is isolated from the OS and applications, it hence shields OS and applications from physical layer variations. In this project, we plan to

  • develop quantitative methods to evaluate the similarity between virtualized system and reference system for real-time applications;
  • develop virtualization methods and techniques for given real-time embedded applications and given many-core platforms that takes into account the trade-offs between different design considerations (feasibility, reliability, and power/thermal, etc.) and objectives; and

•   validate and evaluate the above techniques through both theoretical simulations and practical hardware implementations.